1. Field of the Invention
This invention relates to the field of computer aided design for digital circuits, and particularly to debugging digital circuits constructed using logic or behavioral synthesis. This invention also relates to displaying the results of circuit analysis determined in one domain, such as an annotated netlist of gates, in the context of the circuit structure in another domain, such as the hardware description language (HDL) source text.
2. Statement of the Related Art
A digital circuit designer needs to ensure that the circuit performs the correct function subject to many design constraints. For example, the circuit should perform the correct computation in the proper amount of time. The area that the circuit occupies on a semiconductor die should remain within certain bounds. The power that the circuit consumes while operating should also remain within specified bounds. To be economically manufacturable, the circuit should be testable. An economically useful circuit should not take too long to design, manufacture, test or use.
The digital circuit design process involves translating the designer's sometimes ambiguous thoughts about the function and constraints into the tooling necessary to produce a working circuit. For example, producing a full-custom semiconductor chip requires producing masks that define the deposition of chemicals into a substrate as well as producing test patterns that exercise the final product. As another example of tooling, producing a field programmable gate array requires generating the bit pattern to be downloaded into the chip to specify the configuration of the architecture. Computer Aided Design (CAD) tools facilitate the iterative translation of the designer's developing thoughts into the tooling required to produce a working circuit that satisfies the design constraints. The process of iteratively adjusting a design to meet its requirements is called debugging.
The historical model of the digital design process using conventional CAD tools for a semi-conductor chip is as follows. The designer first conceives of a particular function to implement, as well as constraints such as timing or area that the implementation must meet. Next, historically, the designer mentally transforms the desired function into a high level circuit consisting of components such as gates, adders, registers and RAMS. The designer then captures that insight by drawing a schematic of a circuit that implements that function with a schematic capture tool. The schematic shows how more primitive functional elements, such as gates or transistors, connect together to form more sophisticated functions such as arithmetic logic units. In addition, modern schematic capture tools allow the designer to divide the design hierarchically into interconnected pieces, and then allow the user to specify the details of each of the pieces separately. For example, Design Architect by Mentor Graphics of Wilsonville, Oregon provides these schematic capture functions.
Conventional CAD tools, such as those indicated above, can then take the connections in the schematic and other information to evaluate the circuit and to specify the tooling necessary to construct the circuit. Such tools evaluate the circuit in many ways. For example, commercial CAD tools often have a simulator that predicts the response of the circuit to designer specified input patterns. QuickSim II by Mentor Graphics of Wilsonville, Oreg. is a commonly used simulator. Another common CAD tool is a path delay analyzer that identifies the longest timing path in a circuit design. DesignTime by Synopsys, Inc. of Mountain View, Calif. is a tool that provides path delay analysis.
Conventional CAD tools also have the ability to generate the geometric layout of the circuit with layout tools. Cell3 Ensemble by Cadence of San Jose, Calif. is an example of this type of tool. Layout tools are required to produce masks to make a semi-conductor chip.
Conventional CAD tools also have the ability to check that the circuit meets the design rules, and to identify the location of any errors to the designer. Design rules help ensure that the specified circuit will operate once manufactured.
Conventional CAD tools also are used to determine how testable a circuit is, and to generate test patterns automatically. Showing the designer the parts of the circuit that are not testable allows the designer to make modifications that will increase the probability of making a successful chip or circuit. Generating test patterns automatically allows for more thorough testing of the circuit immediately after manufacturing.
As described above, the concept of debugging a circuit design historically refers to the process by which a circuit designer specified a particular implementation with a schematic capture tool, and then used various circuit evaluation tools to verify that the implementation did what the circuit designer wanted. For example, the designer would use a simulator to determine if the circuit produced appropriate outputs from specified inputs. The designer could use the path delay analyzer to determine whether the current design was fast enough to meet the requirements. The layout tools could inform the designer whether the design would fit in the available space.
When a particular design did not meet the designer's expectations or requirements, the designer then modified the design. For example, if the circuit was too slow, the designer identified the offending circuitry and revamped it to increase performance. If the circuit was too large, then the designer revised the circuit to use fewer or smaller components. If the circuit did not behave as required, the designer changed the components and the interconnections to produce the correct function. Because the conventional CAD tools began the analysis with the captured circuit, the timing or area problems could be readily identified to the designer. Because the designer specified the structure of the circuit, the designer could then thoughtfully make adjustments. However, because historically the designer mentally performed the transformation from desired function to circuit, the CAD tools were limited in their ability to identify functional problems to the designer.
Logic synthesis developed to provide the designer with an automatic mechanism to translate a hardware description language (HDL) description of a desired function to a structural description of a circuit that performed the desired function. Logic synthesis begins with the designer describing the desired function using VHDL, Verilog, or any other logic synthesis source language, to specify the behavior. A translator then converts that description into gates and other circuit structures that directly correspond statement by statement with the designer's description. Theoretically, conventional CAD tools could then evaluate the resulting circuit and develop the appropriate tooling.
However, the circuit created by a statement-by-statement translation is generally large and slow. In logic synthesis, translation is followed by logic optimization. Optimization replaces the directly translated structure with a functionally equivalent, yet improved structure.
Unfortunately, the circuit transformations performed by the logic optimizer usually modifies the structure of the circuit. This results in a circuit that is unrecognizable by the designer. The fact that the designer generally can not recognize the original function performed by the transformed circuit makes debugging synthesized logic difficult. Conventional evaluation tools can determine the timing or area problems in the transformed circuit, but the designer can not relate those problems easily to the HDL source specification. Theoretically, the designer could manually determine what part of the HDL specification caused the problem. With that insight, the designer could make the desired changes at the HDL specification, and resynthesize the entire circuit. If the designer's problem occurred in a part of the circuit that passed through the optimizer with few changes, manual backtracking might work. However, the optimization process generally makes many changes, making it either difficult or impossible to backtrack because many points in the original circuit do not exist in the final circuit.
Alternatively, the designer could simply modify the final circuit directly. This would not allow the designer to resynthesize the design from the HDL specification because the designer's circuit changes would be overwritten by subsequent translation and optimization steps. This would destroy the value gained by using the synthesis approach to design.
There are some existing tools and techniques for determining where and how to modify a HDL source specification. One tool allows the designer to examine a gate in the optimized circuit schematic, and inquire where that gate came from in the HDL source, provided that it directly existed in the source. If the tool could not tell where a gate came from, it would say so. An example of a gate tracing tool is Design Analyzer's source-to-gates function, produced by Synopsys, Inc. of Mountain View, Calif. However, many gates are removed and others are added during the translation and optimization process. The gate tracing tool has not proven to be very useful in helping designers debug circuits because many of the components in a optimized circuit can not be traced back to the HDL source specification.
Another method of debugging a synthesized circuit is to partition the design into hierarchical components, and synthesize and optimize the smaller pieces. Because the synthesis and optimization tools generally do not traverse primary inputs and outputs, such a partitioning can reduce the size of the backtracking problem. However, it has the disadvantage that the designer may have to rewrite functionally correct, but nonetheless problematic, synthesis source code to isolate the troublesome parts of the circuit. In addition, this approach will greatly limit the optimizer's ability to reduce the area and increase the speed of the resulting circuits because the optimizer will be constrained by the designer's partition.
In addition, a designer can be mislead by the results obtained by debugging by partitioning. The designer's bug in the circuit might be that it is too slow or too big. Partitioning the synthesis source to locate the cause will result in a different circuit than the unpartitioned source. Therefore, the problem that the designer is chasing could vanish or be made significantly worse by the debugging process itself.
Conventionally, using a synthesizer to translate a specification into a circut can also raise substantial computational problems to incorporate minor changes into a design late in the design process. For example, a designer could have the design fairly close to completion when the designer discovers the need to make a small functional change, such as inverting a particular signal. Intuitively, one would expect that such a small change would require only a small change in the circuit all the way to the layout level. However, it is quite possible that, with conventional synthesis and optimization tools, a small change could require substantial changes in the circuit and the layout. Currently, a designer can limit this kind of problem by partitioning the design into smaller pieces and thus limiting the effect to the directly implicated pieces. However, as described previously, inappropriate or unduly narrow partitioning can limit the ability of the optimization tools to construct a good circuit.
3. A Conventional Design and Debugging Process Overview
FIG. 1 shows an overview of the conventional process for designing and debugging circuits specified with a Hardware Description Language (HDL). The process begins with the designer writing HDL source code 100. A typical language used for specifying circuits is VHDL which is described in the IEEE Standard VHDL Language Reference Manual available from the Institute of Electrical and Electronic Engineers in Piscataway, N.J., which is hereby incorporated by reference. VHDL stands for Very high speed integrated circuit Hardware Description Language. Another language used for specifying circuits is Verilog that is described in Hardware Modeling with Verilog HDL by Eliezer Sternheim, Rajvir Singh, and Yatin Trivedi, published by Automata Publishing Company, Palo Alto, Calif., 1990, which is hereby incorporated by reference. Verilog is also described in the Verilog Hardware Description Language Reference Manual (LRM), version 1.0, November 1991, which is published by Open Verilog International, and is hereby incorporated by reference. The examples used in this document are in VHDL, but the principles readily apply to other circuit specification languages.
After writing a HDL description of a desired function, the designer then simulates the function 101 embedded in the description with a HDL simulator. An example of a functional simulator is VHDL System Simulator that is available from Synopsys, Inc. of Mountain View, Calif. The functional simulator allows the designer to determine whether the circuit produces correct values in response to inputs without regard to timing, area or power constraints. A functional simulator can perform function-only simulation relatively quickly, thus enabling the designer to determine that the circuit will produce the desired output.
If there is a problem with the function, the designer can fix function problems 102 by examining the simulation output and going back to writing HDL code 100. Functional simulation executes the source specification directly without generating or optimizing circuits. Therefore, problems identified during functional simulation can readily be linked to their cause in the HDL source.
If the designer believes that the described circuit provides the correct function, then designer then specifies constraints for the synthesis process 103, e.g. maximum clocking periods, total circuit area, and maximum power. This part of the process is described in Design Compiler Family Reference Manual, Version 3.1a, which is available from Synopsys, Inc. of Mountain View, Calif. and is hereby incorporated by reference. Examples of Computer Aided Design software that use constraint specification are Synergy by Cadence, and Autologic by Mentor Graphics, and Design Compiler by Synopsys.
After developing constraints, the designer then proceeds to synthesize 104 a circuit from the HDL description produced in the writing HDL 100 step. This step involves translating the description into an initial circuit that correspond directly with the statements in the source HDL. An example of software that performs this function is described in the VHDL Compiler Reference Manual, Version 3.1a, which is available from Synopsys, and is hereby incorporated by reference. After translation, the initial circuit is then optimized into a final circuit that meets the performance constraints established in step 103. Prior to optimization, it is a straight-forward task to identify which circuit element of the initial circuit corresponds to what part of the HDL source code. Conventionally, because of the extensive manipulations performed during the optimization process, such identification after optimization becomes almost impossible except at registers and module interface boundaries.
FIG. 2 shows the intermediate data structures involved in the synthesis process 104. The synthesis process begins with HDL source 900. The translator creates a data structure called a parse tree 901 that represents the organizational structure of the HDL. The translator then turns the parse tree into an initial circuit 902. Russ B. Segal's Master's Thesis, "BDSYN: Logic Design Translator" at the University of California at Berkeley, Memo#UCB/ERL M87/33, describes a such a translator, and is hereby incorporated by reference. United States patent application Ser. No. 07/632,439, filed on Dec. 21, 1990, entitled "Method and Apparatus for Synthesizing HDL Descriptions with Conditional Assignments" by Gregory et al, and commonly assigned to Synopsys, Inc. also describes such a translator, and is hereby incorporated by reference. An example of a tool that does this is version 3.1a of the HDL compiler available from Synopsys, Inc.
An optimizer is used to produce the final circuit 903 from the initial circuit 902. The optimization process is explained in "Logic Synthesis Through Local Transformations" by J. Darringer, W. Joyner, L. Berman, and L. Trevillyan in the IBM Journal of Research and Development, volume 25, number 4, July 1981, pages 272-280, which is hereby incorporated by reference. It is also explained in "LSS: A System for Production Logic Synthesis" by J. Darringer, D. Brand, J. Gerbi, W. Joyner, and L. Trevillyan in the IBM Journal of Research and Development, volume 28, number 5, September 1984, pages 537-545, which is hereby incorporated by reference. It is also explained in "MIS: A Multiple-Level Logic Optimization System" by R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang in the IEEE Transactions on Computer Aided Design, Volume 6, number 6, November 1987, pages 1062-1081, which is hereby incorporated by reference. It is also explained in the Ph.D. dissertation "Logic Synthesis for VLSI Design" by R. Rudell at the University of California at Berkeley in 1989, which is hereby incorporated by reference. The optimization process is also described in the Design Compiler Family Reference Manual, version 3.1a which is available from Synopsys, and is hereby incorporated by reference. An example of software that performs this function is the Design Compiler available from Synopsys, Inc. Other examples of software that performs optimization include Synergy from Cadence, Inc., and AutoLogic by Mentor Graphics.
One approach to optimization is to group one or more initial circuit elements together, and replace those elements with a functionally equivalent collection of elements that has better characteristics than the collection of elements replaced. This results in an intermediate circuit that is functionally equivalent to the original. This intermediate circuit can then some or all of its elements grouped for another replacement. This process is repeated until the optimizer meets the constraints imposed in step 103 of FIG. 1, or is unable to make any further improvement.
Before beginning the optimization process, the components of the initial circuit can be divided into two groups: those components that must be preserved through the optimization process, and those that can be replaced with functional equivalents. For example, a logic optimizer may replace a block of boolean logic with another block so long as function is maintained. Generally, replaceable components can also be eliminated. Examples of components that are generally preserved through the optimization process are primary inputs, primary outputs and registers.
After developing a circuit, the designer can then analyze the circuit 105 using conventional analysis tools, as shown in FIG. 1. For example, the designer could estimate the area that the circuit consumes or what the longest delay path is in the circuit. This analysis can identify problems to the designer. The analysis report 904 is often a text document, as shown in FIG. 2.
After identifying timing, area, testing or power problems with the analysis tools, the designer then devises a means to adjust the circuit to fix these problems 108. Ideally, the designer would go back to the HDL where the function is specified and make adjustments there. However, because it is currently hard to identify the specific places in the source HDL that led to the problem, modifying the appropriate part of the HDL is currently not an effective debugging technique. The designer can usually identify which hierarchical module contains some, of the problem, and the designer could then manually rewrite that module to create more primary inputs and outputs to examine. This is very time consuming and is generally done as a last resort. Alternatively, the designer could adjust the constraints 103 and synthesizes the circuit 104 again to see if the problem is alleviated.
After debugging the circuit, the designer then releases the design for fabrication 106.
4. System Performance
In addition to the debugging problems presented by the transformations made by the logic synthesis process, there are also difficulties associated with efficiently and economically constructing CAD systems that compute and display analysis results. Conceptually, after specifying a design, debugging a circuit involves having the designer repeatedly (1) determine a particular circuit characteristic or property that the designer wants to know about, (2) identify a kind of analysis that will provide information about that characteristic, (3) instruct the CAD system to perform that analysis, (4) display the results of that analysis, and (5) gain insight into the desired characteristic from the display. The designer is interested in completing these steps as quickly as possible. Circuit CAD tools have historically facilitated this goal by making the instruction and display steps computationally efficient. To improve response times, circuit CAD tools have often tightly couple the software that performed the analysis to the software that performed the display function. This was often done by having the display software depend heavily on the data structure used to process or store the results of the analysis.
For example, timing analysis often reveals the portions of the circuit that are too slow. Reviewing this analysis historically has involved examining the schematic and tracing the critical path. However, as described previously, the schematic may have little to do with the designer's specification of the circuit.
This intimate linking of display to analysis causes several problems. First, as described, in conjunction with logic synthesis, displaying the data structure linked with the analysis may not be particularly insightful to the designer. Second, such an intimate linking requires more software development and designer training. If there were N kinds of displays, and M kinds of analysis, and each kind of display could be combined with each kind of analysis, then conventional CAD systems tended to have N*M individual display/analysis programs. This requires the designer to become proficient with a multiplicity of slightly different interfaces as well as requiring the tool supplier to construct all of these tools.
However, modern CAD tools must support the development of chips containing millions of transistors. Designing chips with this many components requires that the CAD tools display and analyze large data structures. Processing large data structures tends to reduce the response time of CAD tools. The conventional technique of tightly coupling the display software to the analysis software helps the CAD system maintain a reasonable response time with the large data structures.
Intimately linking the display tools to the analysis tool data structures poses some problems. First, it tends to require the maker of the CAD tool to produce a large number of products that require support. Second, the variety of such tools tends to introduce variations in the command interface that the designer must use to identify and initiate circuit analysis. Both of these problems lead to frustrated designers and tool builders.
5. Background Conclusion
Using HDL synthesis can simplify the task of circuit design by allowing the designer to specify the required function in an HDL textual description without specifying the details of the circuit implementation. After creating a circuit using synthesis, the designer can use conventional circuit analysis tools to determine characteristics of the final circuit. Conventional analysis will describe such things as the area consumed by different parts of the circuit, or what the longest delay path is through the circuit. Using these analysis results, the designer can then identify which portions of the circuit are problematic. However, because the optimization portion of synthesis often transforms the design substantially, it is difficult, if not impossible, except in certain special cases, to relate specific portions of the final circuit to the HDL source that generated those portions. This inability to trace the circuit analysis results easily to the HDL source represents a substantial barrier for debugging circuits efficiently.